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Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten. Implementation of an asynchronous bundled-data router for a GALS NoC in the context of a VSoC
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Postprint urn:nbn:de:0011-n-4425632 (1.0 MByte PDF) MD5 Fingerprint: d7c1e6261e99c914759cc82b38b296c4 © IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Created on: 6.5.2017 |
| Dietrich, Manfred; Novák, Ondrej ; Fraunhofer-Institut für Integrierte Schaltungen -IIS-, Außenstelle Entwurfsautomatisierung -EAS-, Dresden; Institute of Electrical and Electronics Engineers -IEEE-; IEEE Computer Society:
20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2017. Proceedings : April 19-21, 2017, Dresden, Germany
Piscataway, NJ: IEEE, 2017
ISBN: 978-1-5386-0471-7
ISBN: 978-1-5386-0472-4
pp.199-204 |
| International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) <20, 2017, Dresden> |
| Bundesministerium für Bildung und Forschung BMBF
03ZZ0427E; cSoC3D
Echtzeitfähige 3D-Datenverarbeitung auf kaskadierten analog-digital customized System on a Chip-Architekturen |
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| English |
| Conference Paper, Electronic Publication |
| Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) () |
| Network-on-Chip; low latency; GALS; asynchronous circuits; vision-system-on-chip; CAD; synthesis |
Abstract
Designs of asynchronous networks-on-chip are of growing interest because a complete asynchronous implementation can solve the synchronization problems of large networks. However, asynchronous circuits suffer from the lack of proper design flows because their functionality often relies on timing constraints, which are not extensively supported by common CAD synthesis tools. This paper proposes the design and implementation of an asynchronous router architecture suitable for a network-on-chip in the context of a Vision-System-on-Chip. The developed design flow for the synthesis of asynchronous bundled-data pipelines is based on common synthesis tools and, therefore, enables high compatibility with synchronous designs and a low barrier to entry.