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Transfer-free fabrication of graphene transistors

 
: Wessely, P.J.; Wessely, F.; Birinci, E.; Schwalke, U.; Riedinger, B.

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Postprint urn:nbn:de:0011-n-2116873 (2.0 MByte PDF)
MD5 Fingerprint: 27561c0c5fa0588165e9197681471862
Copyright AIP
Created on: 23.4.2013


Journal of vacuum science and technology B. Microelectronics and nanometer structures 30 (2012), No.3, Art.03D114, 5 pp.
ISSN: 0734-211X
ISSN: 1071-1023
ISSN: 2166-2746
ISSN: 2166-2754
European Commission EC
ESF-EuroGRAPHENE; ELOGRAPH
Deutsche Forschungsgemeinschaft DFG
SCHW1173/7-1
English
Journal Article, Electronic Publication
Fraunhofer IWM ()
graphene transistor; CVD

Abstract
The authors invented a method to fabricate graphene transistors on oxidized silicon wafers without the need to transfer graphene layers. To stimulate the growth of graphene layers on oxidized silicon, a catalyst system of nanometer thin aluminum/nickel double layer is used. This catalyst system is structured via liftoff before the wafer enters the catalytic chemical vapor deposition (CCVD) chamber. In the subsequent methane-based growth process, monolayer graphene field-effect transistors and bilayer graphene field-effect transistors are realized directly on oxidized silicon substrate, whereby the number of stacked graphene layers is determined by the selected CCVD process parameters, e.g., temperature and gas mixture. Subsequently, Raman spectroscopy is performed within the channel region in between the catalytic areas and the Raman spectra of five-layer, bilayer, and monolayer graphene confirm the existence of graphene grown by this silicon-compatible, transfer-free and in situ fabrication approach. These graphene FETs will allow a simple and low-cost integration of graphene devices for nanoelectronic applications in a hybrid silicon CMOS environment.

: http://publica.fraunhofer.de/documents/N-211687.html