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All-screen-printed 120-µM-thin large-area silicon solar cells applying dielectric rear passivation and laser-fired contacts reaching 18% efficiency

 
: Gautero, L.; Hofmann, M.; Rentsch, J.; Lemke, A.; Mack, S.; Seiffe, J.; Nekarda, J.; Biro, D.; Wolf, A.; Bitnar, B.; Sallese, J.M.; Preu, R.

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Postprint urn:nbn:de:0011-n-1983401 (992 KByte PDF)
MD5 Fingerprint: 02f239537ad4568d00b91e09cc906028
© 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Created on: 11.8.2012


Institute of Electrical and Electronics Engineers -IEEE-; IEEE Electron Devices Society:
34th IEEE Photovoltaic Specialists Conference, PVSC 2009. Vol.3 : Philadelphia, Pennsylvania, USA, 7 - 12 June 2009
Piscataway/NJ: IEEE, 2009
ISBN: 978-1-4244-2949-3
ISBN: 1-4244-2949-8
ISBN: 978-1-4244-2950-9
pp.1982-1987
Photovoltaic Specialists Conference (PVSC) <34, 2009, Philadelphia/Pa.>
English
Conference Paper, Electronic Publication
Fraunhofer ISE ()

Abstract
The market need for a lower price per Watt(peak) asks for the development of solar cell designs with a low production cost and a high performance. An approach to reach a high efficiency with a solar cell structure containing a diffused emitter on a p-type silicon wafer is the implementation of a PERC structure on the rear side [1]. This structure gets advantageous to the standard screen printed solar cell when its production cost stays comparable to the latter and offers a higher efficiency [2]. Since this technique can inherently be applied to thinner wafers, an additional advantage comes from the reduced material consumption. The purpose of this work is to introduce a production sequence able to create a PERC structure on thin silicon wafers using steps available in the PV industry or at least close to industrial application. Applying this process on Czochralski (Cz) wafers of 120 mu m thickness, a stable efficiency of 18.0 % was achieved.

: http://publica.fraunhofer.de/documents/N-198340.html