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Methodology of virtual testing of trimmable analog circuits

: Sobe, U.; Böhme, E.; Rooch, K.-H.

Preprint urn:nbn:de:0011-n-1355951 (275 KByte PDF)
MD5 Fingerprint: 6b98d83c51ffdfb979833a210f578e21
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Created on: 10.5.2012

Institute of Electrical and Electronics Engineers -IEEE-:
IEEE 16th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 2010 : Montpellier - La Grande Motte, France, Juni 7-9, 2010
New York, NY: IEEE, 2010
ISBN: 978-1-4244-7791-3
ISBN: 978-1-4244-7792-0
6 pp.
International Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW) <16, 2010, Montpellier>
Conference Paper, Electronic Publication
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
virtual testing; precision analog circuits; reference blocks; trimming analysis; verification

This paper presents a design for test (DFT) methodology focused on high precision analog circuits using trimming methodology. A simulation technique called trimming analysis was derived from the production test process and is used for simulation-based verification of the circuit performances including trimming network and trimming algorithm. The virtual trimming by joint simulation of the test procedure and circuit allows to improve all parts and to maximize yield. The application of the analysis is shown for two different examples.