Stadler, W.W.StadlerEsmark, K.K.EsmarkReynders, K.K.ReyndersZubeidat, M.M.ZubeidatGraf, M.M.GrafWilkening, W.W.WilkeningWillemen, J.J.WillemenQu, N.N.QuMettler, S.S.MettlerEtherton, M.M.EthertonNuernbergk, D.D.NuernbergkWolf, H.H.WolfGieser, H.H.GieserSoppa, W.W.SoppaHeyn, V. deV. deHeynNatarajan, M.M.NatarajanGroeseneken, G.G.GroesenekenMorena, E.E.MorenaStella, R.R.StellaAndreini, A.A.AndreiniLitzenberger, M.M.LitzenbergerPogany, D.D.PoganyGornik, E.E.GornikFoss, C.C.FossKonrad, A.A.KonradFrank, M.M.Frank2022-03-032022-03-032005https://publica.fraunhofer.de/handle/publica/20974110.1016/j.microrel.2004.05.0142-s2.0-19944426303CDM hardening during the development of technology, devices, libraries and finally products differs significantly from the process well-established for HBM. This paper introduces a method on the basis of specialized CDM test structures including protection elements and sensitive monitor elements. These test structures mimic typical CDM-sensitive circuits found by physical failure analysis over the years. Manufactured in five different technologies, structures were assembled in both a regular package and a new package emulator. CDM stress tests, very-fast TLP tests, transient interferometric mapping, device simulation, and failure analysis lead to new insights in the complex interdependencies during CDM and underline the need of CDM-specific test structures.en621Test circuits for fast and reliable assessment of CDM robustness of I/O stagesjournal article