Hoyer, IngoIngoHoyerZaarour, TarekTarekZaarourKhalid, AhmedAhmedKhalidUtz, AlexanderAlexanderUtzSeidl, KarstenKarstenSeidlBrown, Kenneth N.Kenneth N.BrownZahran, Ahmed H.Ahmed H.Zahran2026-03-132026-03-1320249798350351712https://publica.fraunhofer.de/handle/publica/50979010.1109/ICNP61940.2024.108585612-s2.0-85218056013Edge computing is evolving to include heterogeneous compute nodes with distinct characteristics. Graphic processing units (GPU) and field-programmable gate arrays (FPGA) can execute demanding deep learning (DL) tasks while meeting the deadlines of time-sensitive applications. However, FPGAs require reconfiguration to execute different tasks. In this paper, we first demonstrate that FPGAs can be reconfigured in real-time. Additionally, we propose ELEVATE as a novel scheduling algorithm for reconfigurable heterogeneous edge computing platforms targeting Industry 4.0 post-production quality control. ELEVATE design focusses on optimising the reconfiguration of the FPGA unit for heterogeneous quality inspection tasks. Our simulations indicate that ELEVATE reduces task waiting time by up to two orders of magnitude and achieves energy savings of up to 25 % compared to a statically configured FPGA unit.enfalseFPGAHLSoffloadingRISC-VScheudulingconference paper