Lao, Z.Z.LaoBerroth, M.M.BerrothThiede, A.A.ThiedeRieger-Motzer, M.M.Rieger-MotzerKaufel, G.G.KaufelSeibel, J.J.SeibelBronner, WolfgangWolfgangBronnerHülsmann, A.A.HülsmannSchneider, J.J.SchneiderRaynor, B.B.Raynor2022-03-032022-03-031997https://publica.fraunhofer.de/handle/publica/19074310.1049/el:19970180A data decision and a static frequency divider in source coupled FET logic with a supply voltage of 1.5V have been designed and fabricated. Both circuits, using 0.2mu m gate length enhancement and depletion AlGaAs/GaAs-HEMTs (integral of tau = 60/55GHz), operate up to 20 Gbit/s and 17GHz. The power consumption is 24 and 21 mW for the data decision circuit and the static frequency divider together with the output buffer, respectively.enfrequency dividerFrequenzteilerHEMTsupply voltageVersorgungsspannung621667384journal article