Müller, RolandRolandMüllerOppelt, MaximilianMaximilianOppeltKundu, BijoyBijoyKunduAgashe, Bangalore Ramesh AkshayBangalore Ramesh AkshayAgasheThönes, ThomasThomasThönesHerzer, ElmarElmarHerzerSchuhmann, ClaudiaClaudiaSchuhmannChakrabarty, SoumitroSoumitroChakrabartyKroos, ChristianChristianKroosMateu Sáez, María LoretoMaría LoretoMateu Sáez2022-09-262022-09-262022https://publica.fraunhofer.de/handle/publica/42695110.1007/978-3-031-04580-6_262-s2.0-85129810296This paper presents a partial automated workflow for a hardware and software co-design used to generate analog convolutional neural networks. The developed workflow provides an automated generation of the schematic and layout of analog neural networks itself as well as the verification of the created circuit with an automated simulation setup. The designed application-specific integrated circuit (ASIC) has an energy consumption of 450 nJ (235 nJ for the frontend and 215 nJ for the neural network) and needs 369 µs (362 µs for the front-end and 7 µs for the neural network) per inference.enAnalog computingAnalog synthesisHardware and software co-designIntegrated circuitsNeuromorphic computingWorkflowconference paper