Flatt, HolgerHolgerFlattJasperneite, JürgenJürgenJasperneiteSchewe, FrankFrankSchewe2022-03-122022-03-122013https://publica.fraunhofer.de/handle/publica/38230910.1109/ISPCS.2013.66447552-s2.0-84891097916This paper presents an FPGA based Ethernet cut-through switch that is optimized for one-step PTP clock synchronization and fast forwarding of real-time Ethernet frames. Whereas a standard switch ASIC provides sophisticated mechanisms for switching of non-real-time frames, an attached FPGA implements cut-through switching of real-time frames and synchronization events. Moreover, time-stamping of synchronization events, one-step bridge delay compensation, peer-delay responses for power profile and a servo clock are implemented in hardware. The results show that even a low-cost Xilinx Spartan 6 FPGA comprising 47,000 Look-up tables can fulfill the requirements for switching 6 Ethernet ports at 100 Mbps. The combination of cut-through forwarding and transparent one-step clock synchronization yields to bridge delays less than 3 microseconds for both real-time Ethernet data and synchronization events. Therefore, the presented switch can be flexibly integrated into time-synchronized real-time networks in order to provide improved switching functions.enconference paper