Wang, WenWenWangJungk, BernhardBernhardJungkWälde, JulianJulianWäldeDeng, ShuwenShuwenDengGupta, NainaNainaGuptaSzefer, JakubJakubSzeferNiederhagen, RubenRubenNiederhagen2022-03-142022-03-142020https://publica.fraunhofer.de/handle/publica/40643910.1007/978-3-030-38471-5_21We describe a software-hardware co-design for the hash-based post-quantum signature scheme XMSS on a RISC-V embedded processor. We provide software optimizations for the XMSS reference implementation for SHA-256 parameter sets and several hardware accelerators that allow to balance area usage and performance based on individual needs. By integrating our hardware accelerators into the RISC-V processor, the version with the best time-area product generates a key pair (that can be used to generate 210 signatures) in 3.44 s, achieving an over 54× speedup in wall-clock time compared to the pure software version. For such a key pair, signature generation takes less than 10 ms and verification takes less than 6 ms, bringing speedups of over 42× and 17× respectively. We tested and measured the cycle count of our implementation on an Intel Cyclone V SoC FPGA. The integration of our XMSS accelerators into an embedded RISC-V processor shows that it is possible to use hash-based post-quantum signatures for a large variety of embedded applications.enXMSShash-based signaturespost-quantum cryptographyhardware acceleratorFPGARISC-V004005conference paper