Makon, R.E.R.E.MakonDriad, RachidRachidDriadSchneider, K.K.SchneiderLudwig, M.M.LudwigAidam, RolfRolfAidamQuay, RüdigerRüdigerQuaySchlechtweg, M.M.SchlechtwegWeimann, G.G.Weimann2022-03-102022-03-102005https://publica.fraunhofer.de/handle/publica/34792610.1109/CSICS.2005.1531835An 80 Gbit/s monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX) is reported. The integrated circuit (IC) is manufactured using an InP Double Heterostructure Bipolar Transistor (DHBT) technology which features cut-off frequency values of more than 220 GHz for both f(ind T) and f(ind max). The CDR circuit is mainly composed of a half-rate linear phase detector including an 1:2 DEMUX, a loop filter, and a voltage controlled oscillator (VCO). The 40 Gbit/s recovered and demultiplexed data for an 80 Gbit/s input signal feature a signal swing of approximately 600 mV(ind pp). The extracted 40 GHz clock signal shows a phase noise of -98 dBc/Hz at 100 KHz offset frequency. The corresponding peak-to-peak jitter amounts to 1.66 ps while the rms jitter is 0.37 ps. The full IC dissipates 1.65 W at a supply voltage of -4.8 V.enInP-DHBTCDRVCOlinear phase detectorlinearer Phasendetektorloop filterSchleifenfilter621667conference paper