Lopez-Martinez, P.P.Lopez-MartinezHauer, J.J.HauerBlanco-Filgueira, B.B.Blanco-FilgueiraCabello, D.D.Cabello2022-03-042022-03-042009https://publica.fraunhofer.de/handle/publica/21868610.1016/j.sse.2009.01.0182-s2.0-65049089790Enclosed-layout transistors fabricated in standard CMOS processes are known to offer a natural robustness against radiation effects, a characteristic which is boosted in submicron technologies due to the reduction of the oxide thickness. In this paper, a thorough analytical I-V model of short-channel polygonal enclosed-layout transistors is proposed, addressing the issues of drain-induced barrier lowering and threshold voltage roll-off due to short-channel effects. Experimental data is reported, showing good agreement with the theoretical model.en621537journal article