Sturm, R.R.SturmDorner, J.J.DornerReddig, K.K.ReddigSeidelmann, J.J.Seidelmann2022-03-092022-03-092003https://publica.fraunhofer.de/handle/publica/34332110.1109/ASMC.2003.11944782-s2.0-0038519702In this paper we present a simulation study of wafer fab ramp-up scenarios with the simulation software AutoSched AP. A generic factory model (MIMAC 1 from Int. SEMATECH) was adapted to simulate fab ramp-up scenarios. The model was customized to consider time phased modeling capability and time phased reporting. Additionally, an evaluation approach for the comparison of different ramp-up scenarios is presented. This approach helps to evaluate the ramp-up performance with different input parameters. A systematic variation of dispatch rules and lot sizes during ramp-up is shown.enwaferramp upFertigungsanlaufSimulationHalbleiterFertigung670conference paper