Influence of shallow pits and device design of 4H-SiC VDMOS transistors on in-line defect analysis by using PL scanning

Under CopyrightKocher, MatthiasMatthiasKocherSchlichting, HolgerHolgerSchlichtingKallinger, BirgitBirgitKallingerRommel, MathiasMathiasRommelBauer, A.J.A.J.BauerErlbacher, TobiasTobiasErlbacher2022-03-1430.10.20192019https://publica.fraunhofer.de/handle/publica/40542810.24406/publica-fhg-405428en670620530Influence of shallow pits and device design of 4H-SiC VDMOS transistors on in-line defect analysis by using PL scanningposter