Fabrication of gate electrodes for scalable quantum computing using CMOS industry compatible e-beam lithography and numerical simulation of the resulting quantum device

Brackmann, VarvaraVarvaraBrackmannNeul, MalteMalteNeulFriedrich, MichaelMichaelFriedrichLangheinrich, WolframWolframLangheinrichSimon, MaikMaikSimonMuster, PascalPascalMusterPregl, SebastianSebastianPreglDemmler, ArneArneDemmlerHanisch, NorbertNorbertHanischLederer, MaximilianMaximilianLedererZimmermann, KatrinKatrinZimmermannKlos, JanJanKlosReichmann, FelixFelixReichmannYamamoto, YujiYujiYamamotoWislicenus, MarcusMarcusWislicenusDahl, ClausClausDahlSchreiber, Lars R.Lars R.SchreiberBluhm, HendrikHendrikBluhmLilienthal-Uhlig, BenjaminBenjaminLilienthal-Uhlig2023-10-272023-10-272023-10-05https://publica.fraunhofer.de/handle/publica/45221810.1117/12.2675943Universal quantum computers promise the possibility of solving certain computational problems significantly faster than classically possible. For relevant problems, millions of qubits are needed, which is only feasible with industrial production methods. This study presents an electron beam patterning process of gate electrodes for Si/SiGe electron spin qubits, which is compatible with modern CMOS semiconductor manufacturing. Using a pCAR e-beam resist, a process window is determined in which structure sizes of 50 nm line and 30 nm space can be reproducibly fabricated with reasonable throughput. Based on electrostatic simulations, we implemented a feedback loop to investigate the functionality of the gate electrode geometry under fabrication-induced variations.enLithographieCMOSQuantencomputerQuantencomputingIndustrietechnikDDC::600 Technik, Medizin, angewandte Wissenschaften::620 IngenieurwissenschaftenFabrication of gate electrodes for scalable quantum computing using CMOS industry compatible e-beam lithography and numerical simulation of the resulting quantum deviceconference paper