Under CopyrightSchneider, PeterLienig, JensBuhl, RenéHamed, AhmadAhmadHamed2025-05-092025-05-092025-03-28https://doi.org/10.24406/publica-4629https://publica.fraunhofer.de/handle/publica/48747010.24406/publica-4629Analogue to digital data converter (ADC) are main building blocks for many modern electronic systems. To fulfil operation it is important to have a stable clock signal with low variation in frequency. For many portable sensor application low power consumption is crucial as well. Therefore, a well performing clock generation circuit needs to be integrated close to the ADC. The aim of this master thesis is to analysis the design of an integrated oscillator to identify the blocks having critical impact to the system performance. Furthermore, the design shall be optimize for low jitter performance and low power consumption.enlow jitter clock generationphase-locked loop (PLL)000 Informatik, Informationswissenschaft, allgemeine Werkemaster thesis