Nowotny, U.U.NowotnyHurm, V.V.HurmLang, M.M.LangKaufel, U.U.KaufelHülsmann, A.A.HülsmannScheider, J.J.ScheiderJakobus, T.T.JakobusBachem, K.H.K.H.BachemBerroth, M.M.BerrothHoffmann, C.C.HoffmannKöhler, KlausKlausKöhler2022-03-082022-03-081990https://publica.fraunhofer.de/handle/publica/317523A 1:4 demultiplexer circuit has been developed and fabricated using a recessed gate process for enhancement and depletion transistors with 0.5 mym gate length based on a double-delta-doped- quantum well GaAs/AlGaAs structure. The process shows a gate delay of 25 ps at 0.5 mym gate length and 16 ps at 0.3 mym gate length. The demultiplexer was designed in Direct Coupled FET Logic (DCFL). First measurements show a data rate of 4 Gbit/s and a power consumption of 165 mW at 1.5V supply voltage, which is the lowest value published for comparable data rates. This includes five 50 Ohm buffers with 0.8V output voltage swing. A design using 0.3 mym gate length is in process.endemultiplexerfast data communicationfast digital electronicsHEMTsHeterotransisitorheterotransistorlow powerquantum well structuresschnelle Datenübertragungschnelle Digitalelektronik621667conference paper