Defect monitoring and layout related yield and reliability prediction for VLSI interconnects

Dreizner, A.A.DreiznerLukat, KlausKlausLukatPahlitzsch, J.J.PahlitzschKück, H.H.Kück2022-03-092022-03-091994https://publica.fraunhofer.de/handle/publica/322351Based on in-process defect monitor data and layout related Monte Carlo calculations we predict the yield of IC metal layers and the probability that missing metal defects reduce the IC reliability. the influence of such defects on electromigration failure distributions is investigated by experiments on submicron test structures.enAusbeuteAusfallhäufigkeitElektromigrationlayoutLeiterbahnZuverlässigkeit621Defect monitoring and layout related yield and reliability prediction for VLSI interconnectsconference paper