Reiter, D.D.ReiterLi, H.H.LiKnapp, H.H.KnappKammerer, J.J.KammererFritzin, J.J.FritzinMajied, S.S.MajiedSene, B.B.SenePohl, N.N.Pohl2022-03-142022-03-142019https://publica.fraunhofer.de/handle/publica/40754510.1109/BCICTS45179.2019.8972775A 19.5 dBm power amplifier (PA) with a fine power step-size of 0.5 dB for an output power from 5 dBm to 19.5 dBm is designed and implemented in an advanced CMOS technology. This accurate power controlling is achieved by using an 8-bit digitally controlled current source and this ensures also a stable power controlling over the temperature and supply range with a 29 dB dynamic range. The implemented three-stage PA with a device stacking technique has a maximum small signal gain of 43 dB and delivers a maximum saturated output power of 19.5 dBm at 25 °C and 18.5 dBm at 125 °C. The PA core has an area of 0.053 mm 2 and consumes 290 mA including all on-chip biasing circuits from a single 2.1 V power supply. To the best of authors' knowledge, the achieved maximum output power and also the power step-size are record values in advanced bulk CMOS technologies without power combining.en621conference paper