Lopez, P.P.LopezBlanco-Filgueira, B.B.Blanco-FilgueiraPardo, F.F.PardoCabello, D.D.CabelloHauer, J.J.Hauer2022-03-042022-03-042009https://publica.fraunhofer.de/handle/publica/21982610.1088/0268-1242/24/12/1250092-s2.0-77954316968Scaling benefits of CMOS processes include the reduction of the oxide thickness, which in turn favors the reduction of threshold voltage shifts due to radiation-induced gate oxide trapped charge. Moreover, experimental results have shown that this inherent radiation hardness of deep submicron processes can be further exploited using gate-enclosed layout transistors with an annular design. For an in-depth analysis of such structures, we present in this paper a 2D analytical I-V model for short-channel annular devices based on the direct solution of the Poisson equation in cylindrical coordinates. The theoretical approach is confirmed with experimental data in a standard CMOS 0.18 mu m process.en621530journal article