Low-latency image acquisition and processing with a programmable vision-system-on-chip

Under CopyrightDöge, JensJensDögeHoppe, ChristophChristophHoppeReichel, AndreasAndreasReichelPeter, NicoNicoPeterPriwitzer, HolgerHolgerPriwitzer2022-03-1327.6.20182018https://publica.fraunhofer.de/handle/publica/40073910.1109/ISCAS.2018.835184310.24406/publica-r-4007392-s2.0-85057071222This work aims to demonstrate the benefits of using a Vision-System-on-Chip for image processing tasks with very high latency demands between image acquisition and processing. By leveraging a column-parallel, mixed-signal data path, which is entirely software-defined by three application-specific instruction set processors (ASIPs), image data within multiple regions of interest can be analyzed at a frame rate of 10 kHz. Thus, with a delay of 0.35 ms, the trajectory of a moving object is analyzed and the object is precisely deflected using a magnetic actuator.en621004Low-latency image acquisition and processing with a programmable vision-system-on-chipconference paper