Shuto, YusukeYusukeShutoOkuno, JunJunOkunoYonai, TsubasaTsubasaYonaiOno, RyoRyoOnoReinig, PeterPeterReinigLederer, MaximilianMaximilianLedererSeidel, KonradKonradSeidelAlcala, RubenRubenAlcalaMikolajick, ThomasThomasMikolajickSchroeder, Uwe PaulUwe PaulSchroederUmebayashi, TakuTakuUmebayashiAkiyama, KentaroKentaroAkiyama2024-10-092024-10-092024https://publica.fraunhofer.de/handle/publica/47704310.1109/VLSITechnologyandCir46783.2024.106313282-s2.0-85203581470For the first time, a 16-Kbit nonvolatile SRAM (NVSRAM) array based on a metal/ferroelectric/metal capacitor using a sub-10-nm-thick HfZrOx (HZO) layer has been experimentally demonstrated to obtain 100% bit yield. This capacitor is formed using the same integration process as that of a previously developed ferroelectric random-access memory (FeRAM) array on the same wafer. Its sequential operations of nonvolatile data store (Store), cutoff of power supply (power-gating: PG), and data recall (Recall) are completely executed employing a robust Recall sequence, achieving 100%-bit recall after a 200-s PG period at 85 ° C even with sufficiently low operation voltage. The results indicate that our HZO-based NVSRAM and FeRAM hybrid memory system can provide ultra-low power advantages in a System-on-Chip for Internet of Things edge computing.enferroelectric capacitorhafnium oxidenonvolatile SRAMpower-gatingconference paper