Ramm, P.P.RammBonfert, D.D.BonfertGieser, H.H.GieserHaufe, J.J.HaufeIberl, F.F.IberlKlumpp, A.A.KlumppKux, A.A.KuxWieland, R.R.Wieland2022-03-092022-03-092001https://publica.fraunhofer.de/handle/publica/33787810.1109/IITC.2001.930046Vertical System Integration(r) means the realization of three-dimensional integrated systems by thinning, stacking and vertical interchip wiring of completely processed and electrically tested device substrates. The Interchip via (ICV) technology is introduced and discussed as a fully CMOS-compatible wafer-scale process, which provides vertical electrical interchip interconnects placed at arbitrary locations without intervention to the IC's fabrication technologies. Thinning of the device substrate (150 mm) down to 10 mu m as well as bonding it to an other silicon wafer had basically no influence on the electrical performance of EEPROM-products and process monitor structures. Resistances of 2 Ohm for a 2 x 2 mu m2 interchip via contact and working contact chains with 480 interchip via contacts are promising results for the future fabrication of multi-layered three-dimensional systems combining the advantages of different device technologies.en3D-Integrationwafer stackingwafer thinningvertical system integration (VSI)trench etching621conference paper