A 300 mV, low power VCO with the central Frequency of 4.89 GHz in 22 nm FDSOI

Kumar, P.P.KumarBöhme, E.E.BöhmeAl-Eryani, J.J.Al-EryaniBora, P.P.P.P.BoraBorggreve, D.D.BorggreveMaurer, L.L.Maurer2022-03-142022-03-142019https://publica.fraunhofer.de/handle/publica/40883710.1109/APMC46564.2019.9038326A test circuit is presented which generates a frequency spectrum from 4.28 GHz to 5.5 GHz with the tuning percentage of 24.9%. The blocks presented in this paper consists of a Voltage controlled oscillator VCO, interfaced with differential divide by 2, a 2:1 Multiplexer and an output Buffer. All the sub-blocks are designed in 22-nm fully depleted Silicon-on-Insulator (SOI) CMOS technology. In this paper, the architectural design details, simulation and measurement results are presented. The VCO-core operates at the minimum supply voltage of 300 mV, with back-gate-bias voltage of 500 mV and consumes 0.48 mW power. The divided-signal exhibits phase noise performance of -114 dBc/Hz @ 1MHz offset when measured at the central frequency of 5.3 GHz FoMT of -192.7 dBc/Hz.en5GwidebandFDSOIVCOback-gate biasIoTlow power621A 300 mV, low power VCO with the central Frequency of 4.89 GHz in 22 nm FDSOIconference paper