Guiot, EricEricGuiotPicun, GonzaloGonzaloPicunAllibert, FredericFredericAllibertLeib, JürgenJürgenLeibBecker, TomTomBeckerSchwarzenbach, WalterWalterSchwarzenbachDrouin, AlexisAlexisDrouinBéthoux, Jean-MarcJean-MarcBéthouxWidiez, JulieJulieWidiezRouchier, SeverinSeverinRouchierErlbacher, TobiasTobiasErlbacher2022-09-282022-09-282022https://publica.fraunhofer.de/handle/publica/42706410.30420/5658220812-s2.0-85131123379The Smart Cut™ technology enables the integration of a high-quality SiC layer transfer for device yield optimization, combined with a low-resistivity handle wafer (below 5mOhm.cm) to lower device conduction and switching losses. More than 550000 cycles without any failure have been demonstrated during Power Cycling Tests, with a temperature swing of 120K. Evolution of thermal resistance is within the specification of AQG324 standards (2021 revision). This test is a validation of the reliability of our SmartSiC™ engineered substrate.enconference paper