Interconnect challenges for CMOS technology. Materials, processes and reliability for downscaling, packaging and 3D stacking

Dubois, G.2022-03-022022-03-022012978-1-6274-8237-0https://publica.fraunhofer.de/handle/publica/154840Interconnect challenges for CMOS technology. Materials, processes and reliability for downscaling, packaging and 3D stacking