Wolf, M. JürgenM. JürgenWolf2022-03-062022-03-062015https://publica.fraunhofer.de/handle/publica/260546According to the increasing application driven demands on functionality, per-formance, miniaturization and reliability for microelectronic systems, System in Packages (SiP) using 3D integration are key elements for advanced micro-electronic packaging. Key elements for 3D wafer level SiPs are the formation of Through Silicon Vias (TSVs) and their process integration into active devices as well as silicon interposer as a key enabler for 3D Systems.en621book article