SiC MOSFET with a self-aligned channel defined by shallow source-JFET implantation: A simulation study

Under CopyrightSledziewski, TomaszTomaszSledziewskiErlbacher, TobiasTobiasErlbacher2022-03-1421.11.20192019https://publica.fraunhofer.de/handle/publica/40565310.24406/publica-fhg-405653Large cell density within power device is needed to obtain low on state resistance. Cell integration is limited by resolution and overlay accuracy of photolithography. Self-aligned processes, e.g. the self-aligned channel for SiC MOSFET using an over-oxidized polysilicon implantation mask, help to downsale the cell pitch and to increase the cell integration in the device.en670620530SiC MOSFET with a self-aligned channel defined by shallow source-JFET implantation: A simulation studyposter