Under CopyrightKovac, NicolaNicolaKovac2024-02-212024-02-212023-01-24https://publica.fraunhofer.de/handle/publica/462333https://doi.org/10.24406/publica-267310.24406/publica-2673The ability for full layer-by-layer reverse engineering of integrated circuits is key for achieving trust in critical devices from global supply chains. While their feature sizes shrink to few Nanometers the thickness of layers is reduced to some ten Nanometers. One challenge tackling physical and technical limits is to achieve homogeneity across several mm chip dimensions as a prerequisite for further imaging by means of EBeam and IonBeam chip scanning. In this talk we present and discuss today’s methods and results from our CC-EAL6 certified analysis lab and technologies down to 7 nm.enDelayeringReverse engineeringTrusted electronicspresentation