CC BY-NC-ND 4.0Haddadian, SanazSanazHaddadianScheytt, J. ChristophJ. ChristophScheyttBögel, Gerd vomGerd vomBögelGrenter, ThorbenThorbenGrenter2023-10-242023-10-242023-08-29https://publica.fraunhofer.de/handle/publica/452135https://doi.org/10.24406/publica-206310.1109/JRFID.2023.330833210.24406/publica-2063We present a fully integrated radio frequency identifications transponder chip operating at 5.8 GHz, which is compatible with the class-1 generation-2 of the Electronic Product Code protocol (EPC-C1 G2). The tag chip including the analog front-end and the digital baseband processor, are designed in the sub-threshold regime (0.5 V) with a total supply current of less than 50 μA . As a power scavenging unit, a single-stage differential-drive rectifier structure is designed and fabricated with standard threshold voltage (SVT) MOS elements in a commercial 65-nm CMOS process, to provide 0.8 V of rectified voltage. Measurements performed on the fabricated single-stage structure show a maximum power conversion efficiency of 69.6% for a 22 kΩ load and a sensitivity of −12.5 dBm, which corresponds to more than 1 m of reading range. The power conversion efficiency at this range is about 64%.enwireless power transfer (WPT)wireless energy transfer (WET)Internet of Things (IoT)industry 4.0passive RFIDMIMO/MISO readermicrowave RFID transponderRF energy harvestingdynamic threshold cancellation techniquespower/voltage conversion efficiencysub-threshold designjournal article