A 2.5 ns 8x8-b parallel multiplier using 0.5 mym GaAs/GaAlAs heterostructure field effect transistors

Hurm, V.V.HurmNowotny, U.U.NowotnyHülsmann, A.A.HülsmannKaufel, G.G.KaufelRaynor, B.B.RaynorSchneider, J.J.SchneiderBerroth, M.M.BerrothKöhler, KlausKlausKöhler2022-03-032022-03-031991https://publica.fraunhofer.de/handle/publica/17958310.1016/0167-9317(91)90228-6To increase performace of GaAs LSI digital circuits, a 0,5 mym recessed gate process has been developed and utilized for an 8x8-b parallel multiplier. The chip contains about 3000 heterostructure field effect transistors and has a power consumption of 1.5 W. The best results of the maximum multiplication time measured were below 2.5 nsec.enDCFLHFETmultiplierMultiplizierer621667A 2.5 ns 8x8-b parallel multiplier using 0.5 mym GaAs/GaAlAs heterostructure field effect transistorsEin 2.5 ns 8x8-b Parallel-Multiplizierer mit 0.5 mym GaAs/GaAlAs Heterostruktur-Feld-Effekt Transistorenjournal article