Under CopyrightLienig, JensKoh, JeongwookVenkatesha, Shishira SubbaraoShishira SubbaraoVenkatesha2022-03-0711.3.20202020https://publica.fraunhofer.de/handle/publica/28304310.24406/publica-fhg-283043Despite the tremendous advancement in innovations on digitising and processing signals over the last century, real world signals are inevitably analog in nature. A digital-to-analog converter (DAC) serves in translating these digitised signals into different analog quantities like voltage, current or charges. We mainly focus on a Nyquist-rate current-steering digital-to-analog converter (CS-DAC) with resolution scalability from 8 to 12 bit, based upon the required output current for the application. The proposed CS-DAC has a conversion rate of 10 Mega Samples per second (MSps) and adopts a segmented architecture for 8 bit to 12 bit resolution, where optimization is made for achieving a good performance with an area restriction. Especially, a new mode selection decoder is proposed and implemented for the resolution scalability of CS-DAC to 12 bit, 10 bit and 8 bit. The CS-DAC is implemented in a 22 nm Fully Depleted Silicon on Insulator (FDSOI) process and only 0.8 V digital transistors were used for the design. For a typical case of 8 bit resolution, the simulated integral non-linearity (INL) is within 0.05 LSB and the simulated differential non-linearity (DNL) lies between -0.06 and 0.01 LSB providing 7.9 bit accuracy. The10 MSps conversion rate has been obtained by transistor level designed binary-to-thermometer decoder and synchronisation circuit. A spurious-free dynamic range (SFDR) of 57 dB has been obtained for an input signal frequency in the interval from direct current (DC) to Nyquist-rate. The scalable CS-DAC is designed for ultra-low-power application. It has a total DC power consumption of 0.21 mW at 8 bit operation, 0.51 mW at 10 bit operation and 2.4 mW at 12 bit operation. To the best of our knowledge, this is the first demonstration of a DAC capable of scaling its resolution.en621004master thesis