CC BY-NC-ND 4.0Laleni, NellieNellieLaleniMüller, FranzFranzMüllerJang, TaekwangTaekwangJangKämpfe, ThomasThomasKämpfeCuñarro Podestá, Gonzalo FedericoGonzalo FedericoCuñarro Podestá2025-11-142025-11-142024https://publica.fraunhofer.de/handle/publica/499374https://doi.org/10.24406/publica-640910.1109/JXCDC.2024.349561210.24406/publica-64092-s2.0-85209721249This article introduces a 1FeFET-1Capacitance (1F1C) macro based on a 2-bit ferroelectric field-effect transistor (FeFET) cell operating in the charge domain, marking a significant advancement in nonvolatile memory (NVM) and compute-in-memory (CIM). Traditionally, NVMs, such as FeFETs or resistive RAMs (RRAMs), have operated in a single-bit fashion, limiting their computational density and throughput. In contrast, the proposed 2-bit FeFET cell enables higher storage density and improves the computational efficiency in CIM architectures. The macro achieves 111.6 TOPS/W, highlighting its energy efficiency, and demonstrates robust performance on the CIFAR-10 dataset, achieving 89% accuracy with a VGG-8 neural network. These findings underscore the potential of charge-domain, multilevel NVM cells in pushing the boundaries of artificial intelligence (AI) acceleration and energy-efficient computing.entrue1FeFET-1Capacitance (1F1C)artificial intelligence (AI) acceleratorcharge domain computingcompute-in-memory (CIM)ferroelectric field-effect transistor (FeFET)multilevel memory cellsnonvolatile memory (NVM)journal article