Exploration of dual supply voltage logic synthesis in state-of-the-art ASIC design flows

Mahnke, T.T.MahnkeStechele, W.W.StecheleEmbacher, M.M.EmbacherHoeld, W.W.Hoeld2022-03-032022-03-032003https://publica.fraunhofer.de/handle/publica/20322710.5194/ars-1-185-2003en621Exploration of dual supply voltage logic synthesis in state-of-the-art ASIC design flowsjournal article