Under CopyrightVörtler, ThiloThiloVörtlerArndt, ThomasThomasArndtEinwich, KarstenKarstenEinwich2022-03-1226.6.20132013https://publica.fraunhofer.de/handle/publica/38018610.24406/publica-fhg-380186The European Framework 7 project called VERDI (Verification for heterogeneous reliable design and integration started more than one year ago to address the verification and validation (V&V) challenges related to heterogeneous and mixed-signal system design and integration. The VERDI project is currently developing a unified system-level V&V methodology, using industry-recognized standards such as UVM, SystemC/-AMS, and IP-XACT. In this talk, first results of the V&V methodology will be presented with a special focus on how verification scenarios can be reused in the hardware validation phase.en621004presentation