A completely integrated single-chip PLL with a 34 GHz VCO using 0.2 mu m E-/D-HEMT-technology

Lang, M.M.LangLeber, P.P.LeberWang, Z.-G.Z.-G.WangLao, Z.Z.LaoRieger-Motzer, M.M.Rieger-MotzerBronner, WolfgangWolfgangBronnerHülsmann, A.A.HülsmannKaufel, G.G.KaufelRaynor, B.B.Raynor2022-03-092022-03-091997https://publica.fraunhofer.de/handle/publica/32800710.1109/CICC.1997.606682A completely integrated single-chip phase locked loop based on a 0.2 mu m gate length enhancement / depletion AlGaAs/GaAs/ AlGaAs-HEMT technology has been designed and characterized. The chip contains a VCO with 34 GHz center frequency, a dynamic frequency divider by two, a static divider by eight, a phase detector. and a loop fitter.. The chip size is 2.0 x 1.5 mm2. The power consumption is 1.2 W at a supply voltage of -5.0 V. The locking range is approximately +- 700 MHz. The phase noise of locked PLL is -83 dBc/Hz at 100 kHz and -102 dBc/Hz at 1 MHz offset from the carrier frequency, respectively.enPLL 34 GHz621667A completely integrated single-chip PLL with a 34 GHz VCO using 0.2 mu m E-/D-HEMT-technologyEine vollständig integrierte Einchip-PLL mit 34 GHz VCO auf der Basis einer 0.2 Mikrometer E-/D-HEMT-Technologieconference paper