Lerch, W.W.LerchPaul, S.S.PaulNiess, J.J.NiessMcCoy, S.S.McCoySelinger, T.T.SelingerGelpey, J.J.GelpeyCristiano, F.F.CristianoSeverac, F.F.SeveracGavelle, M.M.GavelleBoninelli, S.S.BoninelliPichler, P.P.PichlerBolze, D.D.Bolze2022-03-102022-03-102005https://publica.fraunhofer.de/handle/publica/34806110.1016/j.mseb.2005.08.047A key issue associated with the continuous reduction of dimensions of CMOS transistors is the realization of highly conductive, ultra-shallow junctions for source/drain extensions. Millisecond annealing as an equipment technology provides an ultra-sharp temperature peak of 1.6 ms width which favors dopant activation but nearly suppresses dopant diffusion to form extremely shallow, highly electrically-activated junctions without melting the substrate. On boron beamline implanted wafers the formation of junctions at peak temperatures ranging from 1275 up to 1325 °C was investigated. In the special case of boron, silicon wafers deeply pre-amorphized with Ge were also used. The thermal stability of these boron profile distributions was evaluated by subsequent thermal anneals ranging from 250 to 1050 °C with times from a few seconds to several hundred seconds. From these experiments the deactivation/re-activation mechanism for subsequent annealing can be explained. All the junctions were analyzed by four-point probe measurements; selected samples were analyzed by Hall-effect, secondary ion mass spectrometry (SIMS), and transmission electron microscopy (TEM).enultra-shallow junctionflash-assisted RTPadvanced-logic devicecrystalline and amorphous siliconhall-effect measurementdopant activation and deactivationboron670620530conference paper