Schulz, Stefan E.Prautsch, BenjaminRao, Sunil SatishSunil SatishRao2022-03-072022-03-072015https://publica.fraunhofer.de/handle/publica/280596Due to the shrinkage of MOS transistors in nanometre regime, the basic analog system is becoming difficult to design and the intrinsic precision is getting degraded. In this thesis, the design of an analog block with a digitally assisted circuit in nanometer regime is presented. This digital calibration helps to increase the performance of analog blocks by calibrating the error. In this work, a Miller operational amplifier (Op-Amp) is taken as analog block. This thesis addresses three major tasks: first and second tasks help to reduce the design gap between potential design complexity and designer productivity and the third task helps to increase the performance of the Miller Op-Amp by digital calibration.By employing gm/ID methodology as the fundamental technique, a novel algorithm is presented in this thesis to size the Miller Op-Amps in 180nm and 28nm technology node. This method is beneficial because the sizing of the transistors can be made for low-voltage analog circuits, different transistor specifications as well as for migration and reuse of it. The Miller Op-Amp is analysed and designed by taking specifications like gain, slew rate and gain-bandwidth-product into account. Trade-offs are formulated between circuit parameters and operating region. In addition, a novel approach is presented for migration and reuse of Miller Op-Amps in order to decrease the design gap. This approach combines both constant-inversion-level scaling and channel-length scaling, for easy migration and reuse. Migration of Miller Op-Amps in between these two technology nodes are carried out. These two approaches will enhance the functionality of Intellectual Property Generators by Fraunhofer IIS/EAS, to automate the Miller Op-Amps design and also to migrate it between different technology nodes. To get a better performance by analog circuits in nanometer regime a digital calibration method is employed. Calibration of Miller Op-Amp is realized by dichotomic search algorithm in the feed-back loop to calibrate offset voltage. A new approach is used in the calibration loop in order to increase the resolution of DAC by one bit which in turn decreases in area and power by twofold. A four bit current steering DAC is designed for this calibration circuit in two technology nodes. After calibration, the offset voltage is reduced by the factor of sixteen. Trade-off between calibrated offsets and DAC power consumption are investigated.en621004master thesis