Guiot, EricEricGuiotAllibert, FrédéricFrédéricAllibertLeib, JürgenJürgenLeibBecker, TomTomBeckerSchwarzenbach, WalterWalterSchwarzenbachHellinger, CarstenCarstenHellingerErlbacher, TobiasTobiasErlbacherRouchier, SéverinSéverinRouchier2023-11-162023-11-162023https://publica.fraunhofer.de/handle/publica/45695910.4028/p-777hqg2-s2.0-85163950368The Smart Cut™ technology enables the combination of a high quality single crystal SiC layer onto a low resistivity handle wafer (<5mOhm.cm), allowing device optimization as well as the reduction of device’s conduction and switching losses. On this new SmartSiC™ substrate, the sheet resistance of the back side contact after metal deposition, without anneal, is about 10x lower than the annealed back side contact on 4H-SiC. Schottky-barrier vertical structures thinned down to 250µm were prepared for power cycling tests (PCT) measurements. Up to 250 k cycles, the devices remained within the specifications of AQG324 for samples prepared from SmartSiC™ substrates. We are demonstrating here that in addition to a higher current rating (up to 20%), the SmartSiC™ substrate enables a device fabrication simplification by skipping the annealing of the back-side ohmic contact, without compromising either the back-side contact resistance or the assembly PCsec reliability.enLow resistivityOhmic contactPower CyclingSiC layer transferSmart CutTMSmartSiCTMbook article