Lutz, G.G.LutzBergmann, H.H.BergmannHauff, D.D.HauffHoll, P.P.HollManfredi, P.F.P.F.ManfrediButtler, W.W.Buttler2022-03-082022-03-081987https://publica.fraunhofer.de/handle/publica/315763A 128 channel readout chip suitable for readout with 50 mym pitch has been developed in CMOS technology. It provides signal amplification, parallel data storage and serial readout. Switched capacitor technique is used for noise reduction by multi correlated sampling and simultaneously for second stage amplification. Power consumption is controlled by an externally applied reference voltage thereby allowing for an optimization of speed and noise versus power consumption for the individual needs of the particular experiment. Pulsed mode operation for further reduction of heat dissipation is easily possible without cutting the supply voltages. Very good noise performance (250 + 45.C sub D(pF) electrons) low input impedance (C sub eff bigger than 200pF) and large amplification (70mV/fC) have been obtained at very low power consumption (1.6mW per channel). The chip may be used for both synchronous (e.g. collider) and asynchronous (fixed target) applications where the time of the event is no t known in advance. A second version with only 64 channels suitable for 100 mym pitch is in preparation. Further developments presently under way include the introduction of combined CMOS-JFET technology. (IMS)en621conference paper