Liebsch, W.W.LiebschZier, D.D.Zier2022-03-082022-03-081986https://publica.fraunhofer.de/handle/publica/314585The processor was build in 100 k-ECL technology and the arithmetic unit was integrated in the ECL macrocell array. The processor is connected to peripheral units via three buses and has an interface to host computer-for programme development. The control logic of the processor is built of 100 k-ECL units. Block diagrams of the system and of the processing unit are shown. Peripheral units have separate input/output buses to reduce the reflections. The structure of the two-dimensional DPCM coder and its source file program are shown.encellular arrayscomputerised signal processingemitter-coupled logicmicroprocessor chipsreal-time systemsvideo signalsvideo signal processingecl technologyarithmetic unitmacrocell arrayhost computerprocessing unitsource file program621conference paper