Kraus, S.S.KrausMakon, R.E.R.E.MakonKallfass, I.I.KallfassDriad, RachidRachidDriadMoyal, M.M.MoyalRitter, D.D.Ritter2022-03-112022-03-112010https://publica.fraunhofer.de/handle/publica/36666410.1109/ICIPRM.2010.55159622-s2.0-77955932211We present simulations and measurements of the sensitivity of a master-slave emitter-coupled logic (ECL) latched comparator implemented in an InP/GaInAs DHBT technology. The circuit exhibited simulated and experimental sensitivities of 11.5 mV and 17 mV, respectively, at a clock rate of 20 GHz, with no preamplifier.en667conference paper