Chaudhary, M.W.M.W.ChaudharyHeinig, A.A.HeinigChoubey, B.B.Choubey2022-03-152022-03-152020https://publica.fraunhofer.de/handle/publica/41213610.1109/EPEPS48591.2020.9231389Multi-chip communication interfaces on an interposer or a package substrate must consume minimum routing area while consuming low power in the transceiver blocks. This paper presents an algorithm to design this channel in view of energy and area metrics for a given transceiver topology. It is then show-cased using an example of silicon interposers.en621004conference paper