Realization and evaluation of an ultra low-voltage/low-power 0.25 mu m (n+/p+) dual-workfunction CMOS technology

Schwalke, U.U.SchwalkeBerthold, J.J.BertholdBurenkov, A.A.BurenkovEisele, M.M.EiseleKrieg, R.R.KriegNarr, A.A.NarrSchumann, D.D.SchumannSeibert, R.R.SeibertThanner, R.R.Thanner2022-03-092022-03-091997https://publica.fraunhofer.de/handle/publica/328959The ultimate goal for low power applications is aimed at single-battery operation with a nominal supply voltage of 1.2V and an end-of-life voltage of 0.9V. In this work results on process optimization, device characterization, dynamic performance and hot carrier degradation of an ultra low-power/low-voltage (1.2V) quarter-micron dual-workfunction CMOS technology with low process complexity are presented.enBauelemente-SimulationCMOS-TechnologieCMOS technologydevice simulationDual-Gate-Technologiedual-gate technologydünne GateoxideEnergiesparelektronikLow-Powerlow voltageprocess simulationProzeßsimulationthin gate oxides670620530Realization and evaluation of an ultra low-voltage/low-power 0.25 mu m (n+/p+) dual-workfunction CMOS technologyRealisierung und Evaluierung einer Niedervolt/Energiespar 0.25 mu m (n+/p+) Dual-Gate-CMOS-Technologieconference paper