Lippmann, B.B.LippmannBette, A.-C.A.-C.BetteLudwig, M.M.LudwigMutter, J.J.MutterBaehr, J.J.BaehrHepp, A.A.HeppGieser, HorstHorstGieserKovac, NicolaNicolaKovacZweifel, TobiasTobiasZweifelRasche, M.M.RascheKellermann, O.O.Kellermann2022-10-062022-10-062022https://publica.fraunhofer.de/handle/publica/42737810.23919/DATE54114.2022.97746102-s2.0-85130807075Motivated by the threats of malicious modification and piracy arising from worldwide distributed supply chains, the goal of RESEC is the creation, verification, and optimization of a complete reverse engineering process for integrated circuits manufactured in technology nodes of 40nm and below. Building upon the presentation of individual reverse engineering process stages, this paper connects analysis efforts and yields with their impact on hardware security, demonstrated on a design with implemented experimental hardware Trojans. We outline the interim stage of our research activities and present our future targets linking chip design and physical verification processes.enHardware Reverse EngineeringHardware TrojansImage ProcessingLayout ExtractionRISC-VSEM Imagingconference paper