Perez-Bosch Quesada, EmilioEmilioPerez-Bosch QuesadaRizzi, TommasoTommasoRizziGupta, AdityaAdityaGuptaMahadevaiah, Mamathamba K.Mamathamba K.MahadevaiahSchubert, AndreasAndreasSchubertPechmann, StefanStefanPechmannJia, RuolanRuolanJiaUhlmann, MaxMaxUhlmannHagelauer, AmelieAmelieHagelauerWenger, ChristianChristianWengerPerez, EduardoEduardoPerez2024-03-042024-03-042023https://publica.fraunhofer.de/handle/publica/46278710.1109/CDE58627.2023.10339525This work presents a quasi-static electrical characterization of 1-transistor-1-resistor memristive structures designed following hardness-by-design techniques integrated in the CMOS fabrication process to assure multi-level capabilities in harsh radiation environments. Modulating the gate voltage of the enclosed layout transistor connected in series with the memristive device, it was possible to achieve excellent switching capabilities from a single high resistance state to a total of eight different low resistance states (more than 3 bits). Thus, the fabricated devices are suitable for their integration in larger in-memory computing systems and in multi-level memory applications.enResistanceLayoutVoltageProgrammingLogic gatesin-memory computingCMOS technologyconference paper