Jotschke, MarcelMarcelJotschkeKumaraveeran, PrasathPrasathKumaraveeranBuhl, RenéRenéBuhlZeugmann, BjörnBjörnZeugmann2024-05-272024-05-272023https://publica.fraunhofer.de/handle/publica/46882510.1109/SSI58917.2023.103879562-s2.0-85184821477This paper presents a fully-digital delta-sigma digital-to-analog converter (DAC) for application in audio and hearing aid system-on-chips (SoCs). The slim design is initially synthesized and verified on field programmable gate array (FPGA) hardware, followed by first-time-right production of the integrated circuit in a modern 22 nm FDSOI CMOS technology. Compared to conventional mixed-signal DACs, time-to-product is low, iterative design cycles are reduced, and technology migration is eased and by the fully-digital topology. The circuit operates with a 20 bit input signal bit from serial I2S interface. Audio signal bandwidths up to 8 kHz are supported by the employed 3rd order delta-sigma modulator operating at a clock frequency of 1.024 MHz. We propose two versions of the DAC's interpolation filter with low interpolation ratio of 64. Version one is composed of two half-band filters and a sinc2 filter, and version two employs six half-band filters achieving higher accuracy. In measurements on wafer prober equipment, both design achieve signal-to-noise and distortion ratios of around 80 dBFS with an ultra-low power consumption of 48.8 μ W in best case at a supply voltage of 0.8 V. The data correlate with measurements on FPGA and simulation. The circuit is employed in a digital hearing aid SoC.enaudioDACdigital-to-analog converterhearing aidlow powersigma-deltaconference paper