Desel, T.T.DeselKuttner, F.F.KuttnerKropf, C.C.KropfHaas, M.M.Haas2022-03-092022-03-091997https://publica.fraunhofer.de/handle/publica/327796A 5-bit 150 MS/s full-flash A/D converter with a 32 step adjustable reference circuit is presented. The fully differential architecture with integrated sample/hold circuit significantly improves the performance in a noisy environment. For compatibility a single ended input signals might also applied. This ADC is integrated in a standard 0.7 mm single poly, triple metal CMOS technology at 2.7 V to 3.7 V supply, and dissipates typically 85 mW. Excellent results are achieved with using no more than 0.9 mm2 .enADCADUAnalog-Digital-Umsetzeranalog to digital converterlow powerparallel006621conference paper