Reiner, RichardRichardReinerMönch, StefanStefanMönchWaltereit, PatrickPatrickWaltereitBasler, MichaelMichaelBaslerMüller, StefanStefanMüllerMikulla, MichaelMichaelMikullaQuay, RüdigerRüdigerQuay2023-06-262024-10-222023-06-262023https://publica.fraunhofer.de/handle/publica/44471410.1109/ISPSD57135.2023.10147630This work presents the design, fabrication, and measurements of a GaN-HEMT with a back-gated segment and pull-down pin in a GaN-on-Si technology. The device is designed for the use in high voltage cascodes. The static and dynamic characteristics of the device is demonstrated in a three-stage hybrid cascode assembly. The cascode was measured with a blocking voltage up to 1250 V.enGaN-on-Sicascodescascadesstackingback-gatingself-compatible transistormulti-stage transistor circuitFraunhofer-Leitprojekt ElKaWeconference paper