Giglmayr, J.J.Giglmayr2022-03-082022-03-081984https://publica.fraunhofer.de/handle/publica/313562The common-bus multiprocessor interconnection scheme is considered. The most serious limitations of the single-common bus are its reliability and interference between processors requesting the bus. A relatively simple extension is considered that overcomes these limitations, namely, a multiple bus system arising from duplication, triplication, etc. of the single common bus.encomputer interfacesmultiprocessing systemsoptimisationoptimizationbus systemsloss systemscommon-bus multiprocessor interconnection schemereliabilityinterferencemultiple bus system621conference paper